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january 2012 doc id 022507 rev 1 1/22 AN4015 application note dual-btl class-d audio amplifier demonstration board based on the tda7498e introduction the purpose of this application note is to describe: how to connect the tda7498 demonstration board how to evaluate the performance of the dem onstration board using the electrical curves how to avoid critical issues in the pc b schematic and layout of the tda7498e the tda7498e represents a new generation of analog input class-d devices from stmicroelectronics and is hous ed in a psso36 package. it is able to deliver 160 w +160 w in stereo configuration with v cc = 36 v and a 4 load (a) . figure 1. tda7498e demonstration board a. all of the results and graphs included in this docu ment are measured using audio precision equipment. www.st.com
contents AN4015 2/22 doc id 022507 rev 1 contents 1 overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 2 test conditions and connections of the demonstration board . . . . . . . 5 2.1 power supply and interface connection . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 2.2 output configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 2.3 connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 3 schematic diagram and pcb layout . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 4 electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 5 test curves . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 6 design guidelines for pcb schem atic and layout . . . . . . . . . . . . . . . . 14 6.1 schematic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 6.1.1 main driver for the selection of components . . . . . . . . . . . . . . . . . . . . . 14 6.1.2 decoupling capacitors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 6.1.3 output filter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 6.2 layout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 7 revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
AN4015 list of figures doc id 022507 rev 1 3/22 list of figures figure 1. tda7498e demonstration board . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 figure 2. tda7498e demonstration board connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 figure 3. tda7498e schematic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 figure 4. pcb layout - top side . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 figure 5. pcb layout - bottom side . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 figure 6. pcb layout - top and bottom sides plus components . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 figure 7. thd+n vs. power . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 figure 8. thd+n vs. frequency (ref = 1 w at 1 khz) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 figure 9. dnr . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 figure 10. fft (0 dbr at 1 w) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 figure 11. crosstalk . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 figure 12. linearity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 figure 13. bandwidth . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 figure 14. pout vs. v cc and thd level . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 figure 15. snubber filter - solution 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 figure 16. snubber filter - solution 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 figure 17. dumping network . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 figure 18. frequency shift . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 figure 19. decoupling capacitors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 figure 20. snubber network. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 figure 21. v cc decoupling electrolytic capacitors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 figure 22. rosc - component placement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 figure 23. filter capacitors for svr, vref, svcc, vss and vddpw. . . . . . . . . . . . . . . . . . . . . . . . 19 figure 24. input signal routing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 figure 25. signal ground and power ground routing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
overview AN4015 4/22 doc id 022507 rev 1 1 overview the following terms used in this app lication note are defined as follows: thd+n vs. pout: total harmon ic distortion (thd) plus noise versus output power thd+n vs. freq: total harmonic distortion plus noise versus frequency curve s/n ratio: signal-to-noise ratio dnr: dynamic range fft: fast fourier transform algorithm (method) xtalk: channel separation l to r, or r to l channel crosstalk the equipment used includes the following: audio precision 2722a + aes-17 f ilter + dcx+ aux-0025 filter dc power supply digital oscilloscope (tektronix tds5054b) differential voltage probe (lecroy ap031) current probe (tektronix tcp300) reference documents include: tda7498e datasheet schematic diagram pcb layout te s t c u r ve s
AN4015 test conditions and connections of the demonstration board doc id 022507 rev 1 5/22 2 test conditions and connections of the demonstration board 2.1 power supply and interface connection 1. connect psu to the v cc terminal block 2. connect the analog input cable to the rca connectors on the demonstration board, the other side must be connected to a signal source such as the audio precision analog outputs or a dvd player 2.2 output configuration the tda7498e demonstration board has been configured in 2-channel btl output. 2.3 connections the board terminals (top view of demonstration board) are visible in figure 2 . figure 2. tda7498e demonstration board connections left load right load analog input single-ended input/differential input mode selection standby and mute controls gain selection
schematic diagram and pcb layout AN4015 6/22 doc id 022507 rev 1 3 schematic diagram and pcb layout figure 3. tda7498e schematic
AN4015 schematic diagram and pcb layout doc id 022507 rev 1 7/22 figure 4. pcb layout - top side figure 5. pcb layout - bottom side
schematic diagram and pcb layout AN4015 8/22 doc id 022507 rev 1 figure 6. pcb layout - top and bottom sides plus components
AN4015 electrical characteristics doc id 022507 rev 1 9/22 4 electrical characteristics referring to figure 3: tda7498e schematic , the left (l) and right (r) channels are the output for a stereo configuration. v cc = +36 v, gain 23.6 db; tamb = 25.5 c; inputfreq = 1 khz; reflevel = 1 w (0 dbr), load = 4 (resistive dummy load). table 1. electrical characteristics thd+n vs. power pout = 1 w 0.0555% i ocp 12 a snr no filter -74.3 db aw - filter -77.5 db dnr no filter -94 db aw - filter -98 db xtalk 1 khz -85.9 db
test curves AN4015 10/22 doc id 022507 rev 1 5 test curves figure 7. thd+n vs. power figure 8. thd+n vs. frequency (ref = 1 w at 1 khz) color sweep trac e line style thic k data axis comment 1 1 red solid 2 anlr.thd+n ratio left vcc=36v; load=4ohm; 1khz; ch l 1 3 blue solid 2 anlr.thd+n ratio left vcc=36v; load=4ohm; 1khz; ch r 0.01 10 0.02 0.05 0.1 0.2 0.5 1 2 5 % 1m 400 2m 5m 10m 20m 50m 100m 500m 1 2 5 10 20 50 100 200 w color sweep trac e line style thic k data axis comment 1 1 red solid 2 anlr.thd+n ratio left vcc=36v; 1w@1khz; ch l 1 2 blue solid 2 anlr.thd+n ratio left vcc=36v; 1w@1khz; ch r 0.01 1 0.02 0.05 0.1 0.2 0.5 % 20 20k 50 100 200 500 1k 2k 5k 10k hz
AN4015 test curves doc id 022507 rev 1 11/22 figure 9. dnr figure 10. fft (0 dbr at 1 w) color sweep trac e line style thic k data axis comment 1 1 red solid 2 anlr.thd+n ratio left vcc=36v_1khz_4 ohm; ch l 1 2 blue solid 2 anlr.thd+n ratio left vcc=36v_1khz_4 ohm; ch r 2 1 green solid 2 anlr.thd+n ratio left vcc=36v_1khz_4 ohm; ch r - aw filter 2 2 black solid 2 anlr.thd+n ratio left vcc=36v_1khz_4 ohm; ch l - aw filter -80 -20 -75 -70 -65 -60 -55 -50 -45 -40 -35 -30 -25 d b -60 +0 -55 -50 -45 -40 -35 -30 -25 -20 -15 -10 -5 dbr color sweep trac e line style thic k data axis comment 1 1 red solid 2 fft.ch.1 ampl left vcc=36v; ref: 1w@1khz: ch l 1 2 blue solid 2 fft.ch.2 ampl right vcc=36v; ref: 1w@1khz: ch r -150 +0 -140 -130 -120 -110 -100 -90 -80 -70 -60 -50 -40 -30 -20 -10 d b r b -150 +0 -140 -130 -120 -110 -100 -90 -80 -70 -60 -50 -40 -30 -20 -10 d b r a 20 20k 50 100 200 500 1k 2k 5k 10k hz
test curves AN4015 12/22 doc id 022507 rev 1 figure 11. crosstalk figure 12. linearity color sweep trac e line style thic k data axis comment 1 1 red solid 2 s2c.anlr.crosstalk left vcc=36v; 1w; 4ohm; (ch l on) 1 2 blue solid 2 s2c.anlr.crosstalk left vcc=36v; 1w; 4ohm; (ch r on) -120 +0 -110 -100 -90 -80 -70 -60 -50 -40 -30 -20 -10 d b 20 20k 50 100 200 500 1k 2k 5k 10k hz 0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 2 20 20.5 21 21.5 22 22.5 23 23.5 24 gain linearity input level [v] gain [db] left right
AN4015 test curves doc id 022507 rev 1 13/22 figure 13. bandwidth figure 14. pout vs. v cc and thd level color sweep trac e line style thic k data axis comment 1 1 red solid 2 anlr.level a left vcc=36v; 1w; ch l 1 2 blue solid 2 anlr.level b right vcc=36v; 1w; ch r -3 +1 -2.5 -2 -1.5 -1 -0.5 +0 +0.5 d b r b -3 +1 -2.5 -2 -1.5 -1 -0.5 +0 +0.5 d b r a 10 50k 20 50 100 200 500 1k 2k 5k 10k 20k hz color sweep trac e line style thic k data axis comment 1 1 cyan solid 2 anlr.level a left pout vs. vcc; load=4ohm; thd=1% 2 1 green solid 2 anlr.level a left pout vs. vcc; load=4ohm; thd=10% 3 1 blue solid 2 anlr.level a left pout vs. vcc; load=4ohm; thd=20% 4 1 red solid 2 anlr.level a left pout vs. vcc; load=4ohm; thd=30% 20 200 40 60 80 100 120 140 160 180 w +10 +40 +12.5 +15 +17.5 +20 +22.5 +25 +27.5 +30 +32.5 +35 +37.5 vdc
design guidelines for pcb schematic and layout AN4015 14/22 doc id 022507 rev 1 6 design guidelines for pcb schematic and layout 6.1 schematic 6.1.1 main driver for the selection of components absolute maximum rate (input v cc supply): 40 v bypass capacitor 100 nf in parallel to 1f for each power v cc branch. dielectric x7r is suggested. coil saturation current must be compatible with the peak current of application 6.1.2 decoupling capacitors there are two different ways to use the decoupling capacitors: the decoupling capacitor(s) can be shared among channels; the layout must be designed to implement a "star route" for the v cc paths. one decoupling capacitor can be used for each channel. it is mandatory that each decoupling capacitor be placed as close as possible to the ic pins. this solution is implemented on the tda7498e demonstration board. 6.1.3 output filter snubber network: the key function of a snubber network is to absorb energy from the inductive component in the power circuit (the output coils and the speaker). the purpose of the snubber rc network is to dissipate the unnecessary high pulse energy, such as a high voltage spike, in the powe r circuit which is dangerous to the system. main filter (low-pass filter): the purpose of the main filter is to remove the carrier frequency ( 310 khz) and to cut off the frequency higher than the audible range of 20 khz. the lpf filter is implemented by a passive butterworth topology. in order to have a clean and flat frequency response, it is mandatory to design the filter to fix the cutoff frequency a little bit above 20 khz. damping network: the purpose of the damping network is to avoid the high-frequency oscillation issue on the ou tput circuit. when th e load is disconnected from the amplifier, the frequency response of the main filter is not flat and there is the possibility of adding gain in a frequency band. the damping network also improves the thd performance. the damping network can also avoid the inductive effect of the pcb tracks when the system is working at high frequency with pwm.
AN4015 design guidelines for pcb schematic and layout doc id 022507 rev 1 15/22 snubber filter the snubber circuit must be optimized for the specific application. starting values are 330 pf in series to 22 ohm. the power dissipation of this network (resistor) depends on the power supply, frequency and capacitor values using following formula: this power is dissipated on the series resistance. figure 15. snubber filter - solution 1 to increase the efficiency, it is possible to use two equal snubber networks toward gnd. in this case, the formula to evaluate power is: this power is dissipated on the resistance. figure 16. snubber filter - solution 2 pcf2v ? () 2 ?? = c126 330p r44 22 inxa inxb pcf2v 2 ?? ? = c127 330p c130 330p r45 22 r46 22 inxa inxb
design guidelines for pcb schematic and layout AN4015 16/22 doc id 022507 rev 1 dumping network the c-r-c is a dumping network. it is main ly intended for high inductive loads and for common-mode noise attenuation. figure 17. dumping network pwm output frequency shifting for am band radio sensitivity improvement using a logic control signal (fs) from mcu or from a dsp (3.3 v) it is possible to modify the pwm output frequency. (b) figure 18. frequency shift b. for the pwm frequency calculation fo rmula please refer to the datasheet.
AN4015 design guidelines for pcb schematic and layout doc id 022507 rev 1 17/22 6.2 layout solder 100 nf and 1f bypass ceramic capacitors as close as possible to the related ic pin to avoid the effect due to the parasitic inductive coil generated by the copper wires, it is suggested to use the ceramic capacitor to balance the reactance. it's mandatory to place the ceramic capacitor as close as possible to the related pins. the distance between the capacitor to the related pins is recommended to be within 5 mm. figure 19. decoupling capacitors solder the snubber networks as close as possible to the related ic pin. a high level spike may occur if the snubber network is placed too far from the pins. it's recommended that the distance from the snubber network be within 3 mm which takes into consideration the width of the copper wire. figure 20. snubber network ground pin and vcc pin of 100 nf and 1 f capacitors should be connected to the related ic pin directly snubber network
design guidelines for pcb schematic and layout AN4015 18/22 doc id 022507 rev 1 use electrolytic capacitors first to separate the v cc branches. a "star route" for the v cc supply is suggested to avoid interference between the channels such as when one channel is idle while the other channel is working with a fu ll load. in applications with high output power, another approach is to filter the two channels separately. this solution is implemented in this demonstration board. figure 21. v cc decoupling electrolytic capacitors rosc network: place the rc filter for the rosc pin close to the ic figure 22. rosc - component placement r-c network for rosc
AN4015 design guidelines for pcb schematic and layout doc id 022507 rev 1 19/22 place the filter capacitors for svr, vref, svcc, vss and vddpw close to the ic. figure 23. filter capacitors for svr, vref, svcc, vss and vddpw input signal routing figure 24. input signal routing filter capacitors for vref, svcc and vss filter capacitors for vdds and vddpw filter capacitor for svr
design guidelines for pcb schematic and layout AN4015 20/22 doc id 022507 rev 1 signal ground and power ground routing: the signal ground should be connected to the bulk capacitor negative terminal via a dedica ted copper track; no vias must be present in the connection path. figure 25. signal ground and power ground routing
AN4015 revision history doc id 022507 rev 1 21/22 7 revision history table 2. document revision history date revision changes 09-jan-2012 1 initial release.
AN4015 22/22 doc id 022507 rev 1 please read carefully: information in this document is provided solely in connection with st products. stmicroelectronics nv and its subsidiaries (?st ?) reserve the right to make changes, corrections, modifications or improvements, to this document, and the products and services described he rein at any time, without notice. all st products are sold pursuant to st?s terms and conditions of sale. purchasers are solely responsible for the choice, selection and use of the st products and services described herein, and st as sumes no liability whatsoever relating to the choice, selection or use of the st products and services described herein. no license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted under this document. i f any part of this document refers to any third party products or services it shall not be deemed a license grant by st for the use of such third party products or services, or any intellectual property contained therein or considered as a warranty covering the use in any manner whatsoev er of such third party products or services or any intellectual property contained therein. unless otherwise set forth in st?s terms and conditions of sale st disclaims any express or implied warranty with respect to the use and/or sale of st products including without limitation implied warranties of merchantability, fitness for a parti cular purpose (and their equivalents under the laws of any jurisdiction), or infringement of any patent, copyright or other intellectual property right. unless expressly approved in writing by two authorized st representatives, st products are not recommended, authorized or warranted for use in milita ry, air craft, space, life saving, or life sustaining applications, nor in products or systems where failure or malfunction may result in personal injury, death, or severe property or environmental damage. st products which are not specified as "automotive grade" may only be used in automotive applications at user?s own risk. resale of st products with provisions different from the statements and/or technical features set forth in this document shall immediately void any warranty granted by st for the st product or service described herein and shall not create or extend in any manner whatsoev er, any liability of st. st and the st logo are trademarks or registered trademarks of st in various countries. information in this document supersedes and replaces all information previously supplied. the st logo is a registered trademark of stmicroelectronics. all other names are the property of their respective owners. ? 2012 stmicroelectronics - all rights reserved stmicroelectronics group of companies australia - belgium - brazil - canada - china - czech republic - finland - france - germany - hong kong - india - israel - ital y - japan - malaysia - malta - morocco - philippines - singapore - spain - sweden - switzerland - united kingdom - united states of america www.st.com

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